Recently there has been a rapid increase in research relating to cryogenic operation of electrical and electronic devices, equipment and systems to realize certain performance advantages inherent at cryogenic temperatures, e.g. 77.degree. K. and lower. In certain applications there is need for these electronic devices to respond to temperatures above cryogenic temperatures in case of problems with the maintaining of cryogenic temperatures. A circuit containing MOS devices which are optimized to operate at cryogenic temperatures will suffer degraded operation and then will cease proper functioning altogether as the temperature is elevated toward room temperature.
It is well known in MOS technology that the magnitude of the threshold voltage for both n and p channel MOS transistors is a function of temperature. More specifically, the threshold voltage value of an MOS transistor increases in magnitude as the temperature is lowered. Accordingly, if a particular chip having transistors with a single particular threshold voltage value characteristic is to be operated throughout a wide temperature range, i.e., a temperature range from room temperature to a cryogenic temperature, the threshold voltage excursion due to temperature may be so great as to adversely effect the operating performance of the device at one end or the other of the temperature range.
If a particular MOS transistor is designed to have a threshold voltage which is optimized for cryogenic operation, the MOS transistor will not be able to function properly at room temperature because the rise in temperature will lower the threshold voltage to such an extent that it would not be possible to fully turn it off. Indeed, the overall maximum current at room temperature operation in a chip comprising MOS transistors which are optimized for cryogenic operation could be sufficiently high to destroy the chip circuitry.
On the other hand, if a particular MOS transistor is designed to have a threshold voltage which is optimized for room temperature operation, that transistor's threshold voltage will be set to a higher value than the cryogenic-optimized device above. Accordingly, as temperature is lowered to the cryogenic range from room temperature, the threshold voltage will increase to such an extent that it occupies an undesirably large portion of the device's switching range. This causes a lower drive than would have occurred with a lower threshold voltage transistor. Nevertheless, this higher-threshold transistor, when used in the appropriate logic circuit, will have performed logic functions reliably over the entire temperature range (even though the speed of operation would have been degraded at cryogenic temperatures relative to the cryogenic device.)
It is generally known in the prior art that more than one value for the threshold voltage of a particular n or p channel device type on a chip can be realized by utilizing an additional masked implant of charge for each additional threshold value desired, so that devices having different threshold voltages are produced on the same chip. However, an additional masking step reduces chip yield and thereby increases the manufacturing costs for a multiple threshold value device. Thus, the already known additional masking step process does not provide an acceptable means for providing a chip having MOS transistors with different threshold voltages so that the chip will have viable operation over a wide temperature range.